Description
When compiled to VHDL this example has a port named unsignedField1
and generates an internal signal named \unsignedField1\
.
I'm not sure what the VHDL spec says about escaped names, but Quartus 18.1 thinks those are the same and throws an error.
Vivado seems fine with it though.
module NamingClashes where
import Clash.Prelude
data SomeType = SomeType { boolField :: Bool, unsignedField :: (Unsigned 3) } deriving (Generic,NFDataX)
i = SomeType False 3
topEntity clk rst = withClockResetEnable clk rst enableGen $ mealy @System f i
{-# ANN topEntity
(Synthesize { t_name = "NamingClashes"
, t_inputs = [ PortName "clk", PortName "rst"
, PortProduct "" [ PortName "", PortName "unsignedField1"]
]
, t_output = PortName "result"
}
)#-}
f s x = (new,out)
where
SomeType _ unsignedField = x
new = s{unsignedField = succ unsignedField}
out = unsignedField > 3
Workaround: compile with -fclash-no-escaped-identifiers